Agenda Differential Signaling Definition Voltage Parameters Common mode parameters Differential mode parameters Current mode logic (CML) buffer Relate to parameters Modeling & simulation Timing parameters Clock recovery Embedded clock AC coupling Common mode response Issues with simulation 8B10B encoding DC balanced codes Duty Cycle distortion Cycle Single Ended Signaling All electrical signal circuits require a loop or return path. Single ended signal subject several means of distortions and noise. Ground or reference may move due to switching currents (SSO noise). We touched on this in the ground conundrum class. A single ended receiver only cares about a voltage that is referenced to its own ground. Electromagnetic interference can impose voltage on a single ended signal. Signal passing from one board to another are subject to the local ground disturbance. We can counteract many of these effect by adding more ground. As frequencies increase beyond 1GHz, 80% of the signal will be lost. Review of threshold sensitivity The wave is referenced to either Vcc or Vss. Consequently the effective DC value of the wave will be tied to one of these rails. The wave is attenuated around the effective DC component of the waveform, but the reference does not change accordingly. Hence the clock trigger point between various clock load points is very sensitive to distortion and attenuation. www.m448中国最大的资料库下载