TN-00-06 BYPASS CAPACITOR SELECTION TECHNICAL NOTE BYPASS CAPACITOR SELECTION FOR HIGH- SPEED DESIGNS This article was origina lly published in 1996. an d resist an ce (R1, Rg2, L2, Lg2 in Figu re 1) so th at tran sien t cu rren ts flo win g acro ss th e power bus do n ot cau se excessive n oise at th e power an d gro un d pin s of th e IC. Th erefo re, th e byp ass cap acit or sh ould h ave lo w effect ive series resist an ce (ESR) an d series in duct an ce wh ile h avin g a large en ough cap acit an ce valu e to su pply cu rren t to th e IC durin g swit ch in g. Several fact ors n eed to be co n sid ered wh en select in g lo cal byp ass cap acit ors. Th ese fact ors in clu de select in g th e pro per cap acit or valu e, dielect ric m at erial, geo m - et ry an d th e lo cat io n of th e cap acit or in relat io n to th e IC. Carefu l observan ce of fu n dam en tal prin cip les will det erm in e h ow well th e cap acit or can su ppress swit ch - in g n oise. INTRODUCTION In ord er to gu aran tee bet ter perfo rm an ce fro m h igh - sp eed digit al in tegrat ed circu it s (ICs), m an ufact urers are tigh ten in g power su pply n oise m argin s. Wit h lo wer power su pply n oise m argin s, th e design er n eed s to pay clo ser at ten tio n to lo cal byp ass cap acit or select io n . As bus sp eed s in crease an d swit ch in g tim es decrease, pro per select io n of lo cal byp ass cap acit ors for h igh - sp eed digit al ICs